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| fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos mb90335 series MB90337/f337/v330a n description the mb90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require usb communications. the usb feature supports not only 12-mbps function operation but also minihost operation. it is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support usb communications. while inheriting the at architecture of the f 2 mc* family, the instruction set supports the c language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, long word processing is now available by intro- ducing a 32-bit accumulator. * : f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. n features clock ? built-in oscillation circuit and pll clock frequency multiplication circuit ? oscillation clock the machine clock is the oscillation clock divided into 2 (for oscillation 6 mhz : 3 mhz) clock for usb is 48 mhz machine clock frequency of 6 mhz, 12 mhz or 24 mhz selectable ? minimum execution time of instruction : 41.6 ns (6 mhz oscillation clock, 4-time multiplied : machine clock 24 mhz and at operating v cc = 3.3 v) the maximum memory space:16 mb 24-bit addressing bank addressing (continued) n pac k ag e r 64-pin plastic lqfp (fpt-64p-m09)
mb90335 series 2 (continued) instruction system data types: bit, byte, word, long word addressing mode (23 types) enhanced high-precision computing with 32-bit accumulator enhance multiply/divide instructions with sign and the reti instruction instruction system compatible with high-level language (c language) and multitask ? employing system stack pointer ? instruction set symmetry and barrel shift instructions program patch function (2 address pointer) 4-byte instruction queue interrupt function ? priority levels are programmable ? 20 interrupts data transfer function ? expanded intelligent i/o service function (ei 2 os) : maximum of 16 channels ? m dmac : maximum 16 channels low power consumption mode ? sleep mode (with the cpu operating clock stopped) ? time - base timer mode (with the oscillator clock and time - base timer operating) ? stop mode (with the oscillator clock stopped) ? cpu intermittent operation mode (with the cpu operating at fixed intervals of set cycles) package ? lqfp-64p (fpt-64p-m09 : 0.65 mm pin pitch) process : cmos technology operation guaranteed temperature: - - - - 40 c to + + + + 85 c (0 c to + + + + 70 c when usb is in use) mb90335 series 3 n n n n internal peripheral function (resource) i/o port: max 45 ports time-base timer : 1channel watchdog timer : 1 channel 16-bit reload timer : 1 channel multi-functional timer ? 8/16-bit ppg timer (8-bit 4 channels or 16-bit 2 channels) the period and duty of the output pulse can be set by the program. ? 16-bit pwc timer : 1 channel timer function and pulse width measurement function uart : 2 channels ? equipped with full duplex double buffer with 8-bit lenghth ? asynchronous transfer or clock-synchronous serial (i/o extended serial) transfer can be set. extended i/o serial interface: 1 channel dtp/external interrupt circuit (8 channels) ? activate the extended intelligent i/o service by external interrupt input ? interrupt output by external interrupt input delayed interrupt output module ? output an interrupt request for task switching usb : 1 channel ? usb function (conform to usb 2.0 full speed) ? supports for full speed/endpoint are specifiable up to six. ? dual port ram (the fifo mode is supported). ? transfer type: control, interrupt, bulk or isochronous transfer possible ? usb mini host function i 2 c interface : 1 channel ? supports intel sm bus standards and phillips i 2 c bus standards ? two-wire data transfer protocol specification ? master and slave transmission/reception note : i 2 c licenae : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by phillips. mb90335 series 4 n n n n product lineup 1. mb90335 series * : it is setting of jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the mb2147- 01 or mb2147-20 hardware manual (3.3 emulator-dedicated power supply switching) about details. n packages and product models : yes : no note : for detailed information on each package, see ? n package dimensions?. part number mb90v330a mb90f337 MB90337 type for evaluation built-in flash memory built-in mask rom rom capacity no 64 kbyte ram capacity 28 kbyte 4 kbyte emulator-specific power supply * used bit ? cpu functions number of basic instructions minimum instruction execu- tion time addressing type program patch function maximum memory space : 351 instructions : 41.6 ns / at oscillation of 6 mhz (when 4 times is used : machine clock of 24 mhz) : 23 types : for two address pointers : 16 mbyte ports i/o ports(cmos) 45 ports uart equipped with full-duplex double buffer clock synchronous or asynchronous operation selectable. it can also be used for i/o serial. built-in special baud-rate generator built-in 2 channels 16-bit reload timer 16-bit reload timer operation built-in 1 channel multi-functional timer 8/16-bit ppg timer (8-bit mode 4 channels, 16-bit mode 2 channels) 16-bit pwc timer 1 channel dtp/external interrupt 8 channels interrupt factor : ?l? ? ?h? edge /?h? ? ?l? edge /?l? level /?h? level selectable i 2 c 1 channel extended i/o serial interface 1 channel usb 1 channel usb function (conform to usb 2.0 full speed) usb mini-host function withstand voltage of 5 v 6 ports (excluding vbus and i/o for i 2 c) low power consumption mode sleep mode/timebase timer mode/stop mode/cpu intermittent mode process cmos operating voltage vcc 3.3 v 0.3 v (at maximum machine clock 24 mhz) package MB90337 mb90f337 mb90v330a fpt-64p-m09 (lqfp-0.65 mm) pga-299c-a01 (pga) mb90335 series 5 n n n n pin assignment (top view) (fpt-64p-m09) vbus vss dvm dvp vcc vss hvm hvp vcc hconx p42/sin0 p43/sot0 p44/sck0 p45/sin1 p46/sot1 p47/sck1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vss x1 x0 p24/ppg0 p23 p22 p21 p20 p17 p16 p15 p14 p13 p12 p11 p10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p51 p41/tot0 p40/tin0 p67/int7/sda0 p66/int6/scl0 p65/int5/pwc p64/int4/sck p63/int3/sot p62/int2/sin p61/int1 p60/int0 p27/ppg3 p26/ppg2 p25/ppg1 p50 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p52 p53 vss md2 md1 md0 rst p54 p00 p01 p02 p03 p04 p05 p06 p07 mb90335 series 6 n n n n pin description * : for circuit information, see ? n i/o circuit type?. (continued) pin no. pin name circuit type* status at reset/ function function qfpm09 46 , 47 x0, x1 a oscillation status it is a terminal which connects the oscillator. when connecting an external clock, leave the x1 pin side uncon- nected. 23 rst f reset input external reset input pin. 25 to 32 p00 to p07 i port input (high-z) general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd00 to rd07 = 1) by the pull-up resistor setting register (rdr0). (when the power output is set, it is invalid.) 33 to 40 p10 to p17 i general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd10 to rd17 = 1) by the pull-up resistor setting register (rdr1). (when the power output is set, it is invalid.) 41 to 44 p20 to p23 d general purpose input/output port. 45 p24 d general purpose input/output port. ppg0 functions as output pins of ppg timers ch0. 51 to 53 p25 to p27 d general purpose input/output port. ppg1 to ppg3 functions as output pins of ppg timers ch1 to ch3. 62 p40 h general purpose input/output port. tin0 function as event input pin of 16-bit reload timer. 63 p41 h general purpose input/output port. tot0 function as output pin of 16-bit reload timer. 11 p42 h general purpose input/output port. sin0 functions as a data input pin for uart ch0. 12 p43 h general purpose input/output port. sot0 functions as a data output pin for uart ch0. 13 p44 h general purpose input/output port. sck0 functions as a clock i/o pin for uart ch0. 14 p45 h general purpose input/output port. sin1 functions as a data input pin for uart ch1. 15 p46 h general purpose input/output port. sot1 functions as a data output pin for uart ch1. 16 p47 h general purpose input/output port. sck1 functions as a clock i/o pin for uart ch1. 50 p50 k general purpose input/output port. 64 p51 k general purpose input/output port. 17, 18 p52, p53 k general purpose input/output port. 24 p54 k general purpose input/output port. mb90335 series 7 (continued) * : for circuit information, see ? n i/o circuit type?. pin no. pin name circuit type* status at reset/ function function qfpm09 54, 55 p60, p61 c port input (high-z) general purpose input/output port. (withstand voltage of 5 v) int0, int1 functions as the input pin for external interrupt ch0 and ch1. 56 p62 c general purpose input/output port. (withstand voltage of 5 v) int2 functions as the input pin for external interrupt ch2. sin data input pin for simple serial io. 57 p63 c general purpose input/output port. (withstand voltage of 5 v) int3 functions as the input pin for external interrupt ch3. sot data output pin for simple serial io 58 p64 c general purpose input/output port. (withstand voltage of 5 v) int4 functions as the input pin for external interrupt ch4. sck clock i/o pin for simple serial io. 59 p65 c general purpose input/output port. (withstand voltage of 5 v) int5 functions as the input pin for external interrupt ch5. pwc functions as the pwc input pin. 60 p66 c general purpose input/output port. int6 functions as the input pin for external interrupt ch6. scl0 functions as the input/output pin for i 2 c interface clock. the port output must be placed in high-z state during i 2 c interface operation. 61 p67 c general purpose input/output port. int7 functions as the input pin for external interrupt ch7. sda0 functions as the i 2 c interface data input/output pin. the port out- put must be placed in high-z state during i 2 c interface operation. 1 vbus c vbus input status detection pin of usb cable. 3dvmj usb input (suspend) usb function d - pin. 4 dvp j usb function d + pin. 7 hvm j usb mini host d - pin. 8 hvp j usb mini host d + pin. 10 hconx e high output external pull-up resistor connection pin. 21, 22 md1, md0 b mode input pin input pin for selecting operation mode. 20 md2 g 5vcc ? power supply power supply pin. 9vcc ? power supply pin. 49 vcc ? power supply pin. 2vss ? power supply pin (gnd). 6vss ? power supply pin (gnd). 19 vss ? power supply pin (gnd). 48 vss ? power supply pin (gnd). mb90335 series 8 n n n n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistance : approx. 1 m w ? with standby control b ? cmos hysteresis input c ? hysteresis input ? nch open drain output d ? cmos output ? cmos hysteresis input (with input interception function at standby) note : the i/o ports and internal resources share one output buffer for their outputs. the i/o port and internal resources share one input buffer for their input. e ? cmos output f ? cmos hysteresis input with pull-up ? resistor approx. 50 k w g ? cmos hysteresis input with pull-down ? resistor approx. 50 k w ? flash product is not provided with pull-down resistor. x1 x0 standby control signal clock input hysteresis input nout nch hysteresis input standby control signal pout nout pch nch hysteresis input standby control signal pout nout pch nch hysteresis input hysteresis input mb90335 series 9 (continued) type circuit remarks h ? cmos output ? cmos hysteresis input (with input interception function at standby) with open drain control signal i ? cmos output ?cmos input (with input interception function at standby) programmable pull-up resistor approx. 50 k w j ? usb i/o pin k ? cmos output ?cmos input (with input interception function at standby) pout nout pch nch open drain control signal standby control signal hysteresis input pout nout pch nch ctl cmos input standby control signal d + d - d + input d-input differential input full d + output full d-output low d + output low d-output direction speed pout nout pch nch cmos input standby control signal mb90335 series 10 n n n n handling devices 1. preventing latchup and turning on power supply latchup may occur on cmos ic under the following conditions: 1. if a voltage higher than v cc or lower than v ss is applied to input and output pins. 2. a voltage higher than the rated voltage is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using cmosics, take great care to prevent the occurrence of latchup. 2. treatment of unused pins leaving unused input pins open may cause a malfunction. these pins must therefore be set to a pull-up or pull- down state. 3. about the attention when the external clock is used using external clock 4. treatment of power supply pins (v cc /v ss ) when the device is provided with multiple v cc and v ss pins, be sure to connect all of the power pins to the power supply and ground outside the device to reduce latch-up and unwanted radiation, prevent the strobe signal from malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design reasons. the power supply source should be connected to the v cc and v ss of this device at the lowest possible impedance. it is also advisable to connect a bypass capacitor of approximately 0.1 m f between v cc and v ss near this device. 5. about crystal oscillator circuit noise near the x0/x1 pin may cause the device to malfunction. when designing the artwork for a pc board using the microcontroller, it is strongly advisable to place the x0/x1 and crystal (ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent their writing patterns from crossing other patterns as possible be cause stable operation can be expected with such a layout. 6. caution on operations during pll clock mode even if the oscillator comes off or the clock input stops with the pll clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the pll internal automatic oscillator circuit.performance of this operation, however, cannot be guaranteed. x0 x1 open mb90335 series 11 7. stabilization of supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the v cc supply voltage operating range. for stabilization reference, the supply voltage should be controlled so that v cc ripple variations (peak-to-peak values) at commercial frequencies (50 mhz to 60 mhz) fall below 10 % of the standard v cc supply voltage and the transient regulation does not exceed 0.1 v/ms at temporary changes such as power supply switching. 8. writing to flash memory for serial writing to flash memory, always make sure that the operating voltage v cc is between 3.13 v and 3.6 v. for normal writing to flash memory, always make sure that the operating voltage v cc is between 3.0 v and 3.6 v. mb90335 series 12 n n n n block diagram f 2 mc-16lx cpu ram rom uart/sio ch0, ch1 i2c sio m dmac usb (function) (mini-host) p00 p07 p10 p17 p20 p27 p40 p47 p50 p54 p60 p67 x0, x1 rst md0 to md2 sin0, sin1 sot0, sot1 sck0, sck1 scl0 sda0 int0 to int7 dvp dvm hvp hvm hconx vbus tot0 tin0 ppg0 to ppg3 pwc sin sot sck * : channel for use in 8-bit mode. two channels (ch1, ch3) are used in 16-bit mode. note : i/o ports share pins with peripheral resources. for details, see ? n pin assignment? and ? n pin description?. note also that pins used for peripheral resources cannot serve as i/o ports. 16-bit reload timer external interrupt 16-bit pwc 8/16-bit ppg timer ch0 to ch3* clock control circuit interrupt controller internal data bus i/o port (port 0, 1, 2, 4, 5, 6) mb90335 series 13 n n n n memory map memory map of mb90335 series notes : when the rom mirror function register has been set, the mirror image data at higher addresses (?ff8000 h to ffffff h ? ) of bank ff is visible from the higher addresses (?008000 h to 00ffff h ?) of bank 00. for setting the rom mirror function, see ?16. rom mirror function select module? in ? n peripheral resources?. reference : the rom mirror function is for using the c compiler small model. the lower 16-bit addresses of bank ff are equivalent to those of bank 00. since the rom area in bank ff exceeds 48 kbytes, however, the mirror image of all the data in the rom area cannot be reproduced in bank 00. when the c compiler small model is used, the data table mirror image can be shown at ?008000 h to 00ffff h ? by storing the data table at ?ff8000 h to ffffff h ?. therefore, data tables in the rom area can be referenced without declaring the far addressing with the pointer. ffffff h 00ffff h 007fff h 007900 h 007100 h 008000 h ff0000 h 000100 h 0000fb h 000000 h ffffff h 00ffff h 007fff h 007900 h 001100 h 008000 h ff0000 h 000100 h 0000fb h 000000 h ffffff h 00ffff h 007fff h 007900 h 001100 h 008000 h ff0000 h 000100 h 0000fb h 000000 h mb90v330a mb90f337 MB90337 single chip mode (rom mirror function) peripheral area rom (ff bank) rom area (image of ff bank) register ram area (28 kbytes) peripheral area peripheral area rom (ff bank) rom area (image of ff bank) register ram area (4 kbytes) peripheral area peripheral area rom (ff bank) rom area (image of ff bank) register ram area (4 kbytes) peripheral area mb90335 series 14 n n n n f 2 mc - 16l cpu programming model ? dedicated register ? general purpose registers ? processor status ah al dpr pcb dtb usb ssb adb 8 bit 16 bit 32 bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16 bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70 mb90335 series 15 n n n n i/o map (continued) address register abbreviation register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h prohibited 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 - - - xxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h to 00000f h prohibited 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h prohibited 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 - - - 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h to 00001a h prohibited 00001b h odr4 port 4 output pin register r/w port 4 (od control) 0 0 0 0 0 0 0 0 b 00001c h rdr0 port 0 pull-up resistance register r/w port 0 (pull-up) 0 0 0 0 0 0 0 0 b 00001d h rdr1 port 0 pull-up resistance register r/w port 1 (pull-up) 0 0 0 0 0 0 0 0 b 00001e h prohibited 00001f h 000020 h smr0 serial mode register ch0 r/w uart0 0 0 1 0 0 0 0 0 b 000021 h scr0 serial control register ch0 r/w 0 0 0 0 0 1 0 0 b 000022 h sidr0 serial input data register ch0 r xxxxxxxx b sodr0 serial output data register ch0 w 000023 h ssr0 serial status register ch0 r/w 0 0 0 0 1 0 0 0 b 000024 h utrlr0 uart prescaler reload register ch0 r/w communication prescaler (uart0) 0 0 0 0 0 0 0 0 b 000025 h utcr0 uart prescaler control register ch0 r/w 0 0 0 0 - 0 0 0 b 000026 h smr1 serial mode register ch1 r/w uart1 0 0 1 0 0 0 0 0 b 000027 h scr1 serial control register ch1 r/w 0 0 0 0 0 1 0 0 b 000028 h sidr1 serial input data register ch1 r xxxxxxxx b sodr1 serial output data register ch1 w 000029 h ssr1 serial status register ch1 r/w 0 0 0 0 1 0 0 0 b mb90335 series 16 (continued) address register abbreviation register read/ write resource name initial value 00002a h utrlr1 uart prescaler reload register ch1 r/w communication prescaler (uart1) 0 0 0 0 0 0 0 0 b 00002b h utcr1 uart prescaler control register ch1 r/w 0 0 0 0 - 0 0 0 b 00002c h to 00003b h prohibited 00003c h enir interrupt/dtp enable register r/w dtp/external interrupt 0 0 0 0 0 0 0 0 b 00003d h eirr interrupt/dtp source register r/w 0 0 0 0 0 0 0 0 b 00003e h elvr request level setting register lower r/w 0 0 0 0 0 0 0 0 b 00003f h request level setting register higher r/w 0 0 0 0 0 0 0 0 b 000040 h to 000045 h prohibited 000046 h ppgc0 ppg0 operation mode control register r/w ppg ch0 0x0 0 0xx1 b 000047 h ppgc1 ppg1 operation mode control register r/w ppg ch1 0x0 0 0 0 0 1 b 000048 h ppgc2 ppg2 operation mode control register r/w ppg ch2 0x0 0 0xx1 b 000049 h ppgc3 ppg3 operation mode control register r/w ppg ch3 0x0 0 0 0 0 1 b 00004a h prohibited 00004b h 00004c h ppg01 ppg0 and ppg1 output control register r/w ppg ch0/1 0 0 0 0 0 0xx b 00004d h prohibited 00004e h ppg23 ppg2 and ppg3 output control register r/w ppg ch2/3 0 0 0 0 0 0 xx b 00004f h to 000057 h prohibited 000058 h smcs serial mode control status register r/w extended serial i/o xxxx0 0 0 0 b 000059 h 0 0 0 0 0 0 1 0 b 00005a h sdr serial data register r/w xxxxxxxx b 00005b h sdcr communication prescaler control register r/w communication prescaler 0xxx0 0 0 0 b 00005c h pwcsr pwc control status register r/w 16-bit pwc timer 0 0 0 0 0 0 0 0 b 00005d h 0 0 0 0 0 0 0 x b 00005e h pwcr pwc data buffer register r/w 0 0 0 0 0 0 0 0 b 00005f h 0 0 0 0 0 0 0 0 b 000060 h divr pwc dividing ratio register r/w - - - - - - 0 0 b 000061 h prohibited 000062 h tmcsr0 timer control status register r/w 16-bit reload timer 0 0 0 0 0 0 0 0 b 000063 h xxxx 0 0 0 0 b 000064 h tmr0 16-bit timer register lower r xxxxxxxx b tmrlr0 16-bit reload register lower w xxxxxxxx b 000065 h tmr0 16-bit timer register higher r xxxxxxxx b tmrlr0 16-bit reload register higher w xxxxxxxx b mb90335 series 17 (continued) address register abbreviation register read/ write resource name initial value 000066 h to 00006e h prohibited 00006f h romm rom mirroring function selection register w rom mirror function selection module - - - - - - 1 1 b 000070 h ibsr0 i 2 c bus status register r i 2 c bus interface 0 0 0 0 0 0 0 0 b 000071 h ibcr0 i 2 c bus control register r/w 0 0 0 0 0 0 0 0 b 000072 h iccr0 i 2 c bus clock selection register r/w xx 0 xxxxx b 000073 h iadr0 i 2 c bus address register r/w xxxxxxxx b 000074 h idar0 i 2 c bus data register r/w xxxxxxxx b 000075 h to 00009a h prohibited 00009b h dcsr dma descriptor channel specification register r/w m dmac 0 0 0 0 0 0 0 0 b 00009c h dsrl dma status register lower r/w 0 0 0 0 0 0 0 0 b 00009d h dsrh dma status register higher r/w 0 0 0 0 0 0 0 0 b 00009e h pacsr program address detection control status register r/w address match detection 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt source generate/ release register r/w delayed interrupt - - - - - - - 0 b 0000a0 h lpmcr low power consumption mode register r/w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register r/w clock 1 1 1 1 1 1 0 0 b 0000a2 h prohibited 0000a3 h 0000a4 h dssr dma stop status register r/w m dmac 0 0 0 0 0 0 0 0 b 0000a5 h to 0000a7 h prohibited 0000a8 h wdtc watchdog control register r/w watchdog timer x - xxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/w time-base timer 1 - - 0 0 1 0 0 b 0000aa h prohibited 0000ab h 0000ac h derl dma enable register lower r/w m dmac 0 0 0 0 0 0 0 0 b 0000ad h derh dma enable register higher r/w 0 0 0 0 0 0 0 0 b 0000ae h fmcr flash memory control status register r/w flash memory i/f 0 0 0 x 0 0 0 0 b 0000af h prohibited mb90335 series 18 (continued) address register abbreviation register read/ write resource name initial value 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h hcnt0 usb host control register 0 r/w usb mini host 0 0 0 0 0 0 0 0 b 0000c1 h hcnt1 usb host control register 1 r/w 0 0 0 0 0 0 0 1 b 0000c2 h hirq usb host interruption register r/w 0 0 0 0 0 0 0 0 b 0000c3 h herr usb host error status register r/w 0 0 0 0 0 0 1 1 b 0000c4 h hstate usb host state status register r/w xx 0 1 0 0 1 0 b 0000c5 h hfcomp usb sof interrupt frame compare register r/w 0 0 0 0 0 0 0 0 b 0000c6 h hrtimer usb retry timer setting register 0 r/w 0 0 0 0 0 0 0 0 b 0000c7 h usb retry timer setting register 1 r/w 0 0 0 0 0 0 0 0 b 0000c8 h usb retry timer setting register 2 r/w xxxxxx 0 0 b 0000c9 h hadr usb host address register r/w x 0 0 0 0 0 0 0 b 0000ca h heof usb eof setting register 0 r/w 0 0 0 0 0 0 0 0 b 0000cb h usb eof setting register 1 r/w xx 0 0 0 0 0 0 b 0000cc h hframe usb frame setting register 0 r/w 0 0 0 0 0 0 0 0 b 0000cd h usb frame setting register 1 r/w xxxxx 0 0 0 b 0000ce h htoken usb host token end point register r/w 0 0 0 0 0 0 0 0 b 0000cf h prohibited 0000d0 h udcc udc control register r/w usb function 1 0 1 0 0 0 0 0 b 0000d1 h prohibited mb90335 series 19 (continued) address register abbreviation register read/ write resource name initial value 0000d2 h ep0c ep0 control register r/w usb function x 1 0 0 0 0 0 0 b 0000d3 h r/w xxxx 0 0 0 x b 0000d4 h ep1c ep1 control register r/w 0 0 0 0 0 0 0 0 b 0000d5 h r/w 0 1 1 0 0 0 0 1 b 0000d6 h ep2c ep2 control register r/w 0 1 0 0 0 0 0 0 b 0000d7 h r/w 0 1 1 0 0 0 0 0 b 0000d8 h ep3c ep3 control register r/w 0 1 0 0 0 0 0 0 b 0000d9 h r/w 0 1 1 0 0 0 0 0 b 0000da h ep4c ep4 control register r/w 0 1 0 0 0 0 0 0 b 0000db h r/w 0 1 1 0 0 0 0 0 b 0000dc h ep5c ep5 control register r/w 0 1 0 0 0 0 0 0 b 0000dd h r/w 0 1 1 0 0 0 0 0 b 0000de h tmsp time stamp register r 0 0 0 0 0 0 0 0 b 0000df h r/w 0 0 0 0 0 0 0 0 b 0000e0 h udcs udc status register r/w 0 0 0 0 0 0 0 0 b 0000e1 h udcie interrupt enable register r/w 0 0 0 0 0 0 0 0 b 0000e2 h ep0is ep0i status register r/w xxxxxxxx b 0000e3 h r/w 1 0 xxx 1 xx b 0000e4 h ep0os ep0o status register r/w xxxxxxxx b 0000e5 h r/w 1 0 0 xx 0 0 x b 0000e6 h ep1s ep1 status register r xxxxxxxx b 0000e7 h r/w 1 0 0 0 0 0 0 x b 0000e8 h ep2s ep2 status register r xxxxxxxx b 0000e9 h r/w 1 0 0 0 0 0 0 x b 0000ea h ep3s ep3 status register r xxxxxxxx b 0000eb h r/w 1 0 0 0 0 0 0 x b 0000ec h ep4s ep4 status register r xxxxxxxx b 0000ed h r/w 1 0 0 0 0 0 0 x b 0000ee h ep5s ep5 status register r xxxxxxxx b 0000ef h r/w 1 0 0 0 0 0 0 x b 0000f0 h ep0dt ep0 data register r/w xxxxxxxx b 0000f1 h r/w xxxxxxxx b 0000f2 h ep1dt ep1 data register r/w xxxxxxxx b 0000f3 h r/w xxxxxxxx b 0000f4 h ep2dt ep2 data register r/w xxxxxxxx b 0000f5 h r/w xxxxxxxx b 0000f6 h ep3dt ep3 data register r/w xxxxxxxx b 0000f7 h r/w xxxxxxxx b 0000f8 h ep4dt ep4 data register r/w xxxxxxxx b 0000f9 h r/w xxxxxxxx b mb90335 series 20 (continued) address register abbreviation register read/ write resource name initial value 0000fa h ep5dt ep5 data register r/w usb function xxxxxxxx b 0000fb h r/w xxxxxxxx b 0000fc h to 0000ff h prohibited 000100 h to 001100 h ram area 001ff0 h padr0 program address detection register ch0 lower r/w address match detection xxxxxxxx b 001ff1 h program address detection register ch0 middle r/w xxxxxxxx b 001ff2 h program address detection register ch0 higher r/w xxxxxxxx b 001ff3 h padr1 program address detection register ch1 lower r/w xxxxxxxx b 001ff4 h program address detection register ch1 middle r/w xxxxxxxx b 001ff5 h program address detection register ch1 higher r/w xxxxxxxx b 007900 h prll0 ppg reload register lower ch0 r/w ppg ch0 xxxxxxxx b 007901 h prlh0 ppg reload register higher ch0 r/w xxxxxxxx b 007902 h prll1 ppg reload register lower ch1 r/w ppg ch1 xxxxxxxx b 007903 h prlh1 ppg reload register higher ch1 r/w xxxxxxxx b 007904 h prll2 ppg reload register lower ch2 r/w ppg ch2 xxxxxxxx b 007905 h prlh2 ppg reload register higher ch2 r/w xxxxxxxx b 007906 h prll3 ppg reload register lower ch3 r/w ppg ch3 xxxxxxxx b 007907 h prlh3 ppg reload register higher ch3 r/w xxxxxxxx b 007908 h to 00790b h prohibited 00790c h fwr0 flash program control register 0 r/w flash 0 0 0 0 0 0 0 0 b 00790d h fwr1 flash program control register 1 r/w flash 0 0 0 0 0 0 0 0 b 00790e h ssr0 sector conversion setting register r/w flash 0 0 xxxxx0 b 00790f h to 00791f h prohibited mb90335 series 21 (continued) ? explanation on read/write ? explanation of initial values note : no io instruction can be used for registers located between 007900 h to 007fff h . address register abbreviation register read/ write resource name initial value 007920 h dbapl dma buffer address pointer lower 8-bit r/w m dmac xxxxxxxx b 007921 h dbapm dma buffer address pointer middle 8-bit r/w xxxxxxxx b 007922 h dbaph dma buffer address pointer higher 8-bit r/w xxxxxxxx b 007923 h dmacs dma control register r/w xxxxxxxx b 007924 h dioal dma i/o register address pointer lower 8-bit r/w xxxxxxxx b 007925 h dioah dma i/o register address pointer higher 8-bit r/w xxxxxxxx b 007926 h ddctl dma data counter lower 8-bit r/w xxxxxxxx b 007927 h ddcth dma data counter higher 8-bit r/w xxxxxxxx b 007928 h to 007fff h prohibited r/w read and write enabled r read only w write only 0 : initial value is ?0?. 1 : initial value is ?1?. x : initial value is undefined. - : initial value is undefined (none). mb90335 series 22 n interrupt sources, interrupt vectors, and interrupt control registers interrupt source ei 2 os support m m m m dmac interrupt vector interrupt control register priori- ty number* address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? usb function1 0, 1 #11 0b h ffffd0 h icr00 0000b0 h usb function2 2 to 6 #12 0c h ffffcc h usb function3 #13 0d h ffffc8 h icr01 0000b1 h usb function4 #14 0e h ffffc4 h usb mini-host1 #15 0f h ffffc0 h icr02 0000b2 h usb mini-host2 #16 10 h ffffbc h i 2 c ch0 #17 11 h ffffb8 h icr03 0000b3 h dtp/external interrupt ch0/1 #18 12 h ffffb4 h no ?? #19 13 h ffffb0 h icr04 0000b4 h dtp/external interrupt ch2/3 #20 14 h ffffac h no ?? #21 15 h ffffa8 h icr05 0000b5 h dtp/external interrupt ch4/5 #22 16 h ffffa4 h pwc/reload timer ch0 14 #23 17 h ffffa0 h icr06 0000b6 h dtp/external interrupt ch6/7 #24 18 h ffff9c h no ?? #25 19 h ffff98 h icr07 0000b7 h no ?? #26 1a h ffff94 h no ?? #27 1b h ffff90 h icr08 0000b8 h no ?? #28 1c h ffff8c h no ?? #29 1d h ffff88 h icr09 0000b9 h ppg ch0/1 #30 1e h ffff84 h no ?? #31 1f h ffff80 h icr10 0000ba h ppg ch2/3 #32 20 h ffff7c h no ?? #33 21 h ffff78 h icr11 0000bb h no ?? #34 22 h ffff74 h no ?? #35 23 h ffff70 h icr12 0000bc h no ?? #36 24 h ffff6c h uart (send completed) ch0/ch1 13 #37 25 h ffff68 h icr13 0000bd h extended serial i/o 9 #38 26 h ffff64 h uart(reception completed) ch0/ch1 12 #39 27 h ffff60 h icr14 0000be h time-base timer #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delayed interrupt output module #42 2a h ffff54 h low mb90335 series 23 : available. ei 2 os stop function provided (the interrupt request flag is cleared by the interrupt clear signal. there is a stop demand.) : available (the interrupt request flag is cleared by the interrupt clear signal). : available when any interrupt source sharing icr is not used. : unavailable ? if the same interrupt control register (icr) has two interrupt factors and the use of the ei 2 os is permitted, the ei 2 os is activated when either of the factors is detected. as any interrupt other than the activation factor is masked while the ei 2 os is running, it is recommended that you should mask either of the interrupt requests when using the ei 2 os. ? the interrupt flag is cleared by the ei 2 os interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (icr). note : if a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the m dmac interrupt clear signal. therefore, when you use either of two interrupt factors for the dmac function, another interrupt function is disabled. set the interrupt request permission bit to " 0 " in the appropriate resource, and take measures by software polling. n n n n usb interrupt factor contents usb interrupt factor details usb function 1 end point0-in, endpoint 0-out usb function 2 end point 1-5 usb function 3 voff, von, susp, sof, brst, wkop, cohf usb function 4 spit usb mini-host1 dirq, chhirq, urirq, rwkirq usb mini-host2 sofirq, cmpirq mb90335 series 24 n n n n peripheral resources 1. i/o port ? the i/o ports are used as general-purpose input/output ports (parallel i/o ports). mb90335 series model is provided with 6 ports (45 inputs) . the ports function as input/output pins for peripheral functions also. ? an i/o port, using port data register (pdr) , outputs the output data to i/o pin and input a signal input to i/o port. the port direction register (ddr) specifies direction of input/output of i/o pins on a bit-by-bit basis. ? the following table lists the i/o ports and the peripheral functions with which they share pins. port pin name pin name (peripheral) peripheral function that shares pin port 0 p00 to p07 ? port 1 p10 to p17 ? port 2 p20 to p23 ? p24 to p27 ppg0 to ppg3 8/16 bit ppg timer 0, 1 port 4 p40, p41 tin0, tot0 16-bit reload timer p42 to p47 sin0, sot0, sck0, sin1, sot1, sck1 uart0, 1 port 5 p50 to p54 ? port 6 p60, p61 int0, int1 external interrupt p62 to p64 int2 to int4, sin, sot, sck external interrupt, serial io p65 int5, pwc external interrupt, pwc p66, p67 int6, int7, scl0, sda0 external interrupt, i 2 c mb90335 series 25 register list (port data register) * : r/w access to i/o ports is a bit different in behavior from r/w access to memory as follows: input mode read : the level at the relevant pin is read. write : data is written to the output latch. output mode read : the data register latch value is read. write : data is output to the relevant pin. pdr0 initial value access address : 000000 h xxxxxxxx b r/w* pdr1 address : 000001 h xxxxxxxx b r/w* pdr2 address : 000002 h xxxxxxxx b r/w* pdr4 address : 000004 h xxxxxxxx b r/w* pdr5 address : 000005 h - - - xxxxx b r/w* pdr6 address : 000006 h xxxxxxxx b r/w* 7654 321 0 p06 p07 p05 p04 p03 p02 p01 p00 15 14 13 12 11 10 9 8 p16 p17 p15 p14 p13 p12 p11 p10 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 15 14 13 12 11 10 9 8 ? ?? p54 p53 p52 p51 p50 7654 321 0 p66 p65 p64 p63 p62 p61 p60 p67 mb90335 series 26 register list (port direction register) ? when each pin is serving as a port, the corresponding pin is controlled as follows: 0 : input mode 1 : output mode this bit becomes 0 after a reset. note : if these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to the current input values of the pins. when switching a pin from input port to output port, therefore, write a desired value in the pdr first, then set the ddr to switch the pin for output. register list (port pull-up register) controls the pull-up resistor in input mode. 0 : without pull-up resistor in input mode. 1 : with pull-up resistor in input mode. meaningless in output mode (without pull-up resistor) ./ the input/output register is decided by the setting of the direction register (ddr) . no pull-up resistor is used in stop mode (spl = 1). ddr0 initial value access address : 000010 h 00000000 b r/w ddr1 address : 000011 h 00000000 b r/w ddr2 address : 000012 h 00000000 b r/w ddr4 address : 000014 h 00000000 b r/w ddr5 address : 000015 h - - - 00000 b r/w ddr6 address : 000016 h 00000000 b r/w 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d 00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 15 14 13 12 11 10 9 8 ? ?? d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 rdr0 initial value access address : 00001c h 00000000 b r/w rdr1 address : 00001d h 00000000 b r/w 7654 321 0 rd06 rd07 rd05 rd04 rd03 rd02 rd01 rd00 15 14 13 12 11 10 9 8 rd16 rd17 rd15 rd14 rd13 rd12 rd11 rd10 mb90335 series 27 register list (output pin register) controls open-drain output in output mode. 0 : serves as a standard output port in output mode. 1 : serves as an open-drain output port in output mode. meaningless in input mode. (output high-z) / the input/output register is decided by the setting of the direction register (ddr) . block diagram of port 0 pin and port1 pin block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin odr4 initial value access address : 00001b h 00000000 b r/w 7654 321 0 od46 od47 od45 od44 od43 od42 od41 od40 pull-up resistor setting register (rdrx) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin built-in pull-up resistor standby control (lpmcr : spl = 1) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin standby control (lpmcr : spl = 1) resource output control signal release output resource input mb90335 series 28 2. time-base timer ? the time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock hclk). ? four different time intervals can be selected, for each of which an interrupt request can be generated. ? operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer. interval time of time-base timer notes : hclk : oscillation clock frequency the parenthesized values assume an oscillator clock frequency of 6 mhz. clock cycles supplied from time-base timer notes : hclk : oscillation clock frequency the parenthesized values assume an oscillator clock frequency of 6 mhz. register list note : for the conditions for clearing the time-base timer, refer to the chapter for the time-base timer in the hardware manual. internal count clock cycle interval time 2/hclk (0.33 m s) 2 12 /hclk (approx. 0.68 ms) 2 14 /hclk (approx. 2.7 ms) 2 16 /hclk (approx. 10.9 ms) 2 19 /hclk (approx. 87.4 ms) where to supply clock clock cycle oscillation stabilization wait of main clock 2 13 /hclk (approx. 1.36 ms) 2 15 /hclk (approx. 5.46 ms) 2 17 /hclk (approx. 21.84 ms) watch dog timer 2 12 /hclk (approx. 0.68 ms) 2 14 /hclk (approx. 2.7 ms) 2 16 /hclk (approx. 10.9 ms) 2 19 /hclk (approx. 87.4 ms) time-base timer control register (tbtc) initial value address : 0000a9 h 1--00100 b ( ? )( ? ) ( r/w ) ( r/w ) ( w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( r/w ) resv ? tbie tbof tbr tbc1 tbc0 mb90335 series 29 block diagram actual interrupt request number of time-base timer is as follows: interrupt request number:#40 (28 h ) tbie tbof tbr resv ?? tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 to ppg timer time-base timer counter dividing hclk by 2 to watchdog timer ckscr : mcs = 1 ? 0* 1 counter clear control circuit interval timer selector tbof clear time-base timer control register (tbtc) time-base timer interrupt signal to clock controller oscillation stabilizing wait time selector tbof set ? :unused of :overflow hclk :oscillation clock *1 :switching the machine clock from main clock to pll clock power-on reset stop mode start mb90335 series 30 3. watchdog timer ? the watchdog timer is a timer counter prepared in case programs run out of control. ? the watchdog timer is a 2-bit counter using the time-base timer as the count clock. ? when started, the watchdog timer resets the cpu if it is not cleared before the two-bit counter overflows. interval time of watchdog timer notes : the maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. the watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. when the device is operating with hclk, therefore, clearing the time-base timer lengthens the watchdog reset generation time interval. event that stop the watchdog timer 1 : stop due to a power-on reset 2 : watchdog reset clear factor of watch dog timer 1 : external reset input by rst pin 2 : writing ?0? to the software reset bit 3 : writing ?0? to the watchdog control bit (second and subsequent times) 4 : transition to sleep mode (clearing the watchdog timer, and suspend counting) 5 : transition to time-base timer mode (clearing the watchdog timer, and suspend counting) 6 : transition to stop mode (clearing the watchdog timer, and suspend counting) register list hclk: oscillation clock (6 mhz) min max clock cycle approx. 2.39 ms approx. 3.07 ms 2 14 2 11 / hclk approx. 9.56 ms approx. 12.29 ms 2 16 2 13 / hclk approx. 38.23 ms approx. 49.15 ms 2 18 2 15 / hclk approx. 305.83 ms approx. 393.22 ms 2 21 2 18 / hclk watchdog timer control register (wdtc) initial value address : 0000a8 h x - xxx111 b ( ? ) ( r ) ( r ) ( r ) ( w ) ( w ) ( w ) 7654 3210 ( r ) ponr wrst erst srst wte wt1 wt0 ? mb90335 series 31 block diagram ponr ? wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 clr clr 2 4 watchdog timer control register (wdtc) watchdog timer timer-base timer mode start sleep mode start counter clear control circuit count clock selector 2-bit counter watchdog timer reset generation circuit to internal reset generation circuit clr and start time-base timer counter dividing hclk by 2 hclk: oscillation clock clear stop mode start mb90335 series 32 4. 16 - bit reload timer the 16-bit reload timer has the internal clock mode to be decrement in synchronization with three different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. either can be selected. this timer defines when the count value changes from 0000 h to ffff h as an underflow. the timer therefore causes an underflow when the count reaches [reload register setting +1]. either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. the interrupt can be generated at the counter underflow occurrence so as to correspond to the dtc. register list timer control status register timer control status register (higher) (tmcsr0) timer control status register (lower) (tmcsr0) 16-bit timer register/16-bit reload register tmr0/tmrlr0 (higher) tmr0/tmrlr0 (lower) initial value address : 000063 h xxxx0000 b initial value address : 000062 h 00000000 b initial value address : 000065 h xxxxxxxx b initial value address : 000064 h xxxxxxxx b ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ??? csl1 csl0 mod2 mod1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 oute ( r/w ) mod0 outl reld inte uf cnte trg ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 d14 ( r/w ) d15 d13 d12 d11 d10 d09 d08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 d06 ( r/w ) d07 d05 d04 d03 d02 d01 d00 mb90335 series 33 block diagram tmrlr0 tmr0 clk tin0 uf en tot0 clk 3 3 2 ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg * 2 internal data bus 16-bit reload register 16-bit timer register reload signal reload control circuit wait signal output control circuit output signal generation circuit pin valid clock decision circuit clock selector operating control circuit select signal external clock internal clock input control circuit pin prescaler count clock generation circuit gate input timer control status register (tmcsr0) interrupt request output #23 (17 h )*1 select function clear trriger machine clock f *1 : interrupt number *2 : underflow mb90335 series 34 5. multifunction timer ? the multifunction timer can be used for waveform output, input pulse width measurement, and external clock cycle measurement. configuration of a multi-functional timer 8/16 bit ppg timer (8 bit : 4 channels, 16 bit : 2 channels) 8/16 bit ppg timer consists of a 8 bit down counter (pcnt) , ppg control register (ppgc0 to ppgc3) , ppg clock control register (pcs01, pcs23) and ppg reload register (prll0 to prll3, prlh0 to prlh3) . when used as an 8/16 bit reload timer, the ppg timer serves as an event timer. it can also output pulses of an arbitrary duty ratio at an arbitrary frequency. ? 8 bit ppg mode each channel operates as an independent 8 bit ppg. ? 8 bit prescaler + 8 bit ppg mode operates as an arbitrary-cycle 8 bit ppg with ch0 (ch2) operating as an 8 bit prescaler and ch2 (ch3) counted by the borrow output of ch0 (ch2). ? 16 bit ppg mode operates as a 16 bit ppg with ch0 (ch2) and ch1 (ch3) connected. ? ppg operation the ppg timer outputs pulses of an arbitrary duty ratio (the ratio between the high and low level periods of pulse waveform) at an arbitrary frequency. can also be used as a d/a converter by an external circuit. 8/16 bit ppg timer 16 bit pwc timer 8 bit 4 ch (16 bit 2 ch) 1 ch mb90335 series 35 register list ppg operation mode control register (ppgc1/ppgc3) (ppgc0/ppgc2) ppg output control register (ppg01/ppg23) ppg reload register (prlh0 to prlh3) (prll0 to prll3) address : 000047 h 000049 h initial value 0x000001 b address : 000046 h 000048 h initial value 0x000xx1 b address : 00004c h 00004e h initial value 000000xx b address : 007901 h 007903 h 007905 h 007907 h initial value xxxxxxxx b address : 007900 h 007902 h 007904 h 007906 h initial value xxxxxxxx b 15 14 13 12 11 10 9 8 ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ? pen1 pe10 pie1 puf1 md1 md0 reserved 7654 3210 ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ? pen0 pe0o pie0 puf0 ?? reserved 7654 321 0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) pcs1 pcs2 pcs0 pcm2 pcm1 pcm0 reserved reserved 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) d14 d15 d13 d12 d11 d10 d09 d08 7654 321 0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) d06 d07 d05 d04 d03 d02 d01 d00 mb90335 series 36 8 bit ppg ch0/2 block diagram ppg0/2 pen0 irq pie0 puf0 prll prlhb prll s rq pcnt (down counter) peripheral clock 16 ppg 0/2 output latch count clock selector timebase counter output main clock 512 ch1/3/5 borrow l/h selector ppgc0 (operation mode control) * : interrupt number to interrupt #30 (1e h )* #32 (20 h )* l/h selector ppg 0/2 output enable peripheral clock 8 peripheral clock 4 peripheral clock 2 peripheral clock a/d converter l data bus h data bus mb90335 series 37 8 bit ppg ch1/3 block diagram ppg1/3 pen1 irq pie1 puf1 prll prlhb prll s rq pcnt0 (down counter) peripheral clock 16 ppg 1/3 output latch count clock selector timebase counter output main clock 512 l/h selector ppgc0 (operation mode control) * : interrupt number to interrupt #30 (1e h )* #32 (20 h )* l/h selector ppg 1/3 output enable peripheral clock 8 peripheral clock 4 peripheral clock 2 peripheral clock l data bus h data bus mb90335 series 38 pwc timer the pwc timer is a 16 bit multifunction up-count timer capable of measuring the input signal pulse width. register list pwc control status register (pwcsr) pwc data buffer register (pwcr) ratio of dividing frequency control register (divr) initial value address : 00005d h 0000000x b initial value address : 00005c h 00000000 b initial value address : 00005f h 00000000 b initial value address : 00005e h 00000000 b initial value address : 000060 h ------ 00 b ( r/w ) ( r ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r/w ) 15 14 13 12 11 10 9 8 stop ( r/w ) strt edir edie ovir ovie err reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 cks0 ( r/w ) cks1 pis1 pis0 s/c mod2 mod1 mod0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 d14 ( r/w ) d15 d13 d12 d11 d10 d9 d8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ????? div1 div0 mb90335 series 39 block diagram err pwcr 16 16 cks1/cks0 15 err cks0/cks1 pis0/pis1 pwcsr divr 2 2 2 2 3 pwc pwcr read error detection reload data transfer over- flow 16 bit up-count timer clock internal clock (machine clock/4) clock devider control circuit timer clear count enable divider clear flag set etc... control bit output start edge selection measurement termination edge end edge selection edge detection divider on/off measurement starting edge overflow interrupt request divide ratio select 8-bit divider f 2 mc-16 bus measurement termination interrupt request input waveform comparator mb90335 series 40 6. uart overview of uart ? uart is a general purpose serial communication interface for synchronous or asynchronous (start-stop syn- chronization) communications with external devices. ? it supports bi-directional communication (normal mode) and master/slave communication (multi-processor mode: supported on master side only). ? an interrupt can be generated upon completion of reception, detection of a reception errror, or upon completion of transmission. ei 2 os is supported also. uart functions uart, or a generic serial data communication interface that sends and receives serial data to and from other cpu and peripherals, has the functions listed in following. note : in clock synchronous transfer mode, the uart transfers only data with no start or stop bit added. uart operation modes ? : setting disabled *1 : + 1 is an address/data setting bit (a/d) which is used for communication control. *2 : only one bit can be detected as a stop bit at reception. operation mode data length synchronization stop bit length without parity with parity 0 normal mode 7 bits or 8 bits asynchronous 1 bit or 2 bits * 2 1 multi processor mode 8 + 1 * 1 ? asynchronous 2 normal mode 8 ? synchronous no function data buffer full-duplex double-buffered transmission mode ? clock synchronous (without start/stop bit) ? clock asynchronous (start-stop synchronous) baud rate ? special-purpose baud-rate generator it is optional from eight kinds. ? baud rate by external clock (clock of sck0/sck1 terminal input) data length ? 8 bits or 7 bits (in the asynchronous normal mode only) ? 1 to 8 bits (in the synchronous mode only) signaling system non return to zero (nrz) system reception error detection ? framing error ? overrun error ? parity error (not supported in operation mode 1) interrupt request ? receive interrupt (reception completed, reception error detected) ? transmission interrupt (transmission completed) ? both the transmission and reception support ei 2 os. master/slave type communication function (multi processor mode) capable of 1 (master) to n (slaves) communication (available just as master) mb90335 series 41 register list serial mode register (smr0, smr1) serial control register (scr0, scr1) serial input/output register (sidr0, sidr1 / sodr0, sodr1) serial data register (ssr0, ssr1) uart prescaler reload register (utrlr0, utrlr1) uart prescaler control register (utcr0, utcr1) 000020 h 000026 h initial value address : 00100000 b 000021 h 000027 h initial value address : 00000100 b 000022 h 000028 h initial value address : xxxxxxxx b 000023 h 000029 h initial value address : 00001000 b 000024 h 00002a h initial value address : 00000000 b 000025 h 00002b h initial value address : 0000 - 000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 md0 ( r/w ) md1 sckl m2l2 m2l1 scke soe m2l0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 p ( r/w ) pen sbl cl a/d rec rxe txe ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( r ) ( r ) ( r ) ( r ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ore ( r ) pe fre rdrf tdre bds rie tie ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( r/w ) ( r/w ) ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 srst ( r/w ) md cks ? d10 d9 d8 reserved mb90335 series 42 ~ block diagram md1 md0 sckl m2l2 m2l1 m2l0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre bds rie tie sidr0, sidr1 sck0, sck1 sot0, sot1 #39 (27 h ) * #37 (25 h ) * sin0, sin1 sodr0, sodr1 smr0 , smr1 scr0 , scr1 ssr0 , ssr1 reception complete control bus special-purpose baud-rate generator (uart prescaler control register utcr0, 1) clock selector receive status decision circuit reception error occurrence signal for ei 2 os (to cpu) reception clock reception control circuit start bit detection circuit reception bit counter reception parity counter shift register for reception internal data bus transmission clock reception interrupt signal transmission control circuit transmission start circuit transmission bit counter transmission parity counter shift register for transmission start transmission * : interrupt number send interrupt signal pin pin pin mb90335 series 43 7. extended i/o serial interface the extended i/o serial interface is a serial i/o interface that can transfer data through the adoption of 8-bit 1 channel configured clock synchronization scheme. lsb-first or msb-first transfer mode can be selected for data transfer. there are two serial i/o operation modes available: ? internal shift clock mode: transfer data in synchronization with the internal clock. ? external shift clock mode: transfer data in synchronization with the clock supplied via the external pin (sck). by manipulating the general-purpose port sharing the external pin (sck) in this mode, data can also be transferred by a cpu instruction. register list serial mode control status register (smcs) serial data register (sdr) communication prescaler control register (sdcr) initial value address : 000059 h 00000010 b initial value address : 000058 h xxxx0000 b initial value address : 00005a h xxxxxxxx b initial value address : 00005b h 0xxx0000 b 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ??? mode bds soe scoe ( ? ) ( ? ) ( ? ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 d7 d5 d4 d3 d2 d1 d0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( r/w ) md ?? div3 div2 div1 div0 mb90335 series 44 block diagram sin sot sck smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe (msb first) d0 to d7 d7 to d0 (lsb first) sdr (serial data register) internal clock internal data bus transfer direction selection read write control circuit shift clock counter interrupt request internal data bus initial value mb90335 series 45 8. i 2 c interface the i 2 c interface is a serial i/o port supporting the inter ic bus. it serves as a master/slave device on the i 2 c bus and has the following features. ? master/slave sending and receiving ? arbitration function ? clock synchronization function ? slave address and general call address detection function ? detecting transmitting direction function ? start condition repeated generation and detection function ? bus error detection function register list i 2 c bus status register (ibsr0) i 2 c bus control register (ibcr0) i 2 c bus clock selection register (iccr0) i 2 c bus address register (iadr0) i 2 c bus data register (idar0) initial value address : 000070 h 00000000 b initial value address : 000071 h 00000000 b initial value address : 000072 h xxx0xxxx b initial value address : 000073 h xxxxxxxx b initial value address : 000074 h xxxxxxxx b ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 rsc ( r ) bb al lrb trx aas gca fbt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 beie ( r/w ) ber scc mss ack gcaa inte int ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ? en cs4 cs3 cs2 cs1 cs0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 a6 ( ? ) ? a5 a4 a3 a2 a1 a0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 mb90335 series 46 block diagram iccr en iccr ibsr bb rsc lrb last bit trx fbt al ibcr ber beie inte int ibcr scc mss ack gcaa ibsr idar iadr aas gca cs4 cs3 cs2 cs1 cs0 2 4 8 16 128 256 32 64 56 78 sync first byte irq scl0 sda0 i 2 c enable clock devide 2 clock selector 2 bus busy repeat start send/receive start stop condition generation arbitration lost detection interrupt request start master ack enable gc-ack enable slave slave address compare end error shift clock edge change timing start stop condition detection generating shift clock f 2 mc-16 bus clock devide 1 clock selector 1 peripheral clock global call mb90335 series 47 9. usb function the usb is an interface supporting the usb (universal serial bus) communications protocol. feature of usb function ? conform to usb 2.0 full speed ? full speed (12 mbps) is supported. ? the device status is auto-answer. ? bit stripping, bit stuffing, and automatic generation and check of crc5 and crc16. ? toggle check by data synchronization bit. ? automatic response to all standard commands except get/setdescriptor and synchframe commands (these three commands can be processed the same way as the class vendor commands). ? the class vendor commands can be received as data and responded via firmware. ? supports up to maximum six endpoints (endpoint0 is fixed to control transfer). ? two transfer data buffers integrated for each end point (one in buffer and one out buffer for end point 0). ? supports automatic transfer mode for transfer data via dma (except buffers for endpoint0). ? capable of detection of connection and disconnection by monitoring the usb bus power line. register list (continued) udc control register (udcc) ep0 control register (ep0c) ep1 control register (ep1c) initial value address : 0000d0 h 10100000 b initial value address : 0000d2 h x1000000 b initial value address : 0000d3 h xxxx0000 b initial value address : 0000d4 h 00000000 b initial value address : 0000d5 h 01100001 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 resum ( r/w ) rst hconx ustp rfbk pwc reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks0 ( r/w ) pks0 pks0 pks0 pks0 pks0 pks0 reserved ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ??? stal reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks1 ( r/w ) pks1 pks1 pks1 pks1 pks1 pks1 pks1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 type ( r/w ) epen type dir dmae nule stal pks1 mb90335 series 48 (continued) ep2/3/4/5 control register (ep2c ? ep5c) time stamp register (tmsp) udc status register (udcs) interrupt enable register (udcie) ep0i status register (ep0is) initial value address : 0000d6 h 0000d8 h 01000000 b 0000da h 0000dc h initial value address : 0000d7 h 0000d9 h 01100000 b 0000db h 0000dd h initial value address : 0000de h 00000000 b initial value address : 0000df h 00000000 b initial value address : 0000e0 h 00000000 b initial value address : 0000e1 h 00000000 b initial value address : 0000e2 h xxxxxxxx b initial value address : 0000e3 h 10xxx1xx b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks2 ~ 5 ( r/w ) pks2 ~ 5 pks2 ~ 5 pks2 ~ 5 pks2 ~ 5 pks2 ~ 5 pks2 ~ 5 reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 type ( r/w ) epen type dir dmae nule stal reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 tmsp ( r ) tmsp tmsp tmsp tmsp tmsp tmsp tmsp ( ? )( ? )( ? )( ? ) ( r ) ( r ) ( r ) 15 14 13 12 11 10 9 8 ? ( ? ) ? ??? tmsp tmsp tmsp ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 von ( r/w ) voff susp sof brst wkup setp conf ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r/w ) 15 14 13 12 11 10 9 8 vonie ( r/w ) voffie suspie sofie brstie wkupie confn confie ( ? )( ? )( ? )( ? )( ? )( ? )( ? ) 76543210 ? ( ? ) ?????? ? ( r/w ) ( ? )( ? )( ? ) ( r/w ) ( ? )( ? ) 15 14 13 12 11 10 9 8 drqiie ( r/w ) bfini ??? drqi ?? mb90335 series 49 (continued) ep0o status register (ep0os) ep1 status register (ep1s) ep2/3/4/5 status register (ep2s to ep5s) ep0/1/2/3/4/5 data register (ep0dt to ep5dt) initial value address : 0000e4 h xxxxxxxx b initial value address : 0000e5 h 100xx00x b initial value address : 0000e6 h xxxxxxxx b initial value address : 0000e7 h 1000000x b initial value address : 0000e8 h 0000ea h xxxxxxxx b 0000ec h 0000ee h initial value address : 0000e9 h 0000eb h 1000000x b 0000ed h 0000ef h 0000f0 h 0000f2 h initial value address : 0000f4 h 0000f6 h xxxxxxxx b 0000f8 h 0000fa h 0000f1 h 0000f3 h initial value address : 0000f5 h 0000f7 h xxxxxxxx b 0000f9 h 0000fb h ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( ? ) ? size size size size size size ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 drqoie ( r/w ) bfini spkie ?? drqo spk ? ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 size ( r/w ) size size size size size size size ( r/w ) ( r/w ) ( ? ) ( r ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 drqie ( r/w ) bfini spkie ? busy drq spk size ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 size ( ? ) ? size size size size size size ( r/w ) ( r/w ) ( ? ) ( r ) ( r/w ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 drqie ( r/w ) bfini spkie ? busy drq spk ? ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 bfdt ( r/w ) bfdt bfdt bfdt bfdt bfdt bfdt bfdt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 bfdt ( r/w ) bfdt bfdt bfdt bfdt bfdt bfdt bfdt mb90335 series 50 10. usb mini - host usb mini-host provides minimal host operations required and is a function that enables data to be transferred to and from device without pc intervention. feature of usb mini - host ? automatic detection of low speed/full speed transfer ? low speed/full speed transfer support ? automatic detection of connection and cutting device ? reset sending function support to usb-bus ? support of in/out/setup/sof token ? in-token handshake packet automatic transmission (excluding stall) ? handshake packet automatic detection at out-token ? supports a maximum packet length of 256 bytes ? error (crc error/toggle error/time-out) various supports ? wake-up function support differences between the usb host and usb mini-host : supported : not supported host mini-host hub support transfer bulk transfer control transfer interrupt transfer iso transfer transfer speed low speed full speed pre packet support sof packet support error crc error toggle error time-out maximum packet < receive data detection of connection and cutting of device transfer speed detection mb90335 series 51 register list (continued) usb host control register 0 (hcont0) usb host control register 1 (hcont1) usb host interruption register (hirq) usb host error status register (herr) usb host state status register (hstate) usb sof interruption frame comparison register (hfcomp) usb retry timer setting register 0/1/2 (hrtimer) initial value address : 0000c0 h 00000000 b initial value address : 0000c1 h 00000001 b initial value address : 0000c2 h 00000000 b initial value address : 0000c3 h 00000011 b initial value address : 0000c4 h xx010010 b initial value address : 0000c5 h 00000000 b initial value address : 0000c6 h 00000000 b initial value address : 0000c7 h 00000000 b initial value address : 0000c8 h xxxxxx00 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 urire ( r/w ) rwkire cmpire cnnire dire sofire urst host ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) sofstep cancel retry reserved reserved reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ( r/w ) tcan rwkirq urirq cmpirq cnnirq dirq sofirq reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rerr ( r/w ) lstsof tout crc tgerr stuff hs hs ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r ) 76543210 ? ( ? ) ? alive clksel sofbusy susp tmode cstat ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) frame comp frame comp frame comp frame comp frame comp frame comp frame comp frame comp ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 rtimer0 ( r/w ) rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rtimer1 ( r/w ) rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ????? rtimer2 rtimer2 mb90335 series 52 (continued) usb host address register (hadr) usb eof setting register 0/1 (heof) usb frame setting register (hframe) usb token end point register (htoken) initial value address : 0000c9 h x0000000 b initial value address : 0000ca h 00000000 b initial value address : 0000cb h xx000000 b initial value address : 0000cc h 00000000 b initial value address : 0000cd h xxxxx000 b initial value address : 0000ce h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 address ( ? ) ? addressaddressaddressaddressaddressaddress ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 eof0 ( r/w ) eof0 eof0 eof0 eof0 eof0 eof0 eof0 ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ? eof1 eof1 eof1 eof1 eof1 eof1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 frame0 ( r/w ) frame0 frame0 frame0 frame0 frame0 frame0 frame0 ( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ? ??? frame1 frame1 frame1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 tknen ( r/w ) tggl tknen tknen endpt endpt endpt endpt mb90335 series 53 11. dtp/external interrupt circuit feature of dtp/external interrupt circuit dtp (data transfer peripheral)/external interrupt circuit detects the interrupt request input from the external interrupt input terminal int7 to int0, and outputs the interrupt request. dtp/external interrupt circuit function the dtp/external interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (int7 to int0). if cpu accept the interrupt request, and if the extended intelligent i/o service (ei 2 os) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (dtp function) performed by ei 2 os. and if ei 2 os is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (dtp function) performed by ei 2 os. feature of dtp/external interrupt circuit register list external interrupt dtp function input pin 8 channels (p60/int0, p61/int1, p62/int2/sin, p63/int3/sot, p64/int4/sck, p65/int5/pwc, p66/int6/scl0, p67/int7/sda0) interrupt source the detection level or the type of the edge for each terminals can be set in the request level setting register (elvr) input of ?h? level/ ?l? level/rising edge/falling edge. interrupt number #18 (12 h ) , #20 (14 h ) , #22 (16 h ) , #24 (18 h ) interrupt control enabling/prohibit the interrupt request output using the dtp/interrupt enable register (enir) interrupt flag holding the interrupt source using the dtp/interrupt cause register (eirr) process setting prohibit ei 2 os (icr: ise=?0?) enable ei 2 os (icr: ise=?1?) process branched to the interrupt handling routine after an automatic data transfer by ei 2 os, branched to the interrupt handling routine interrupt/dtp enable register (enir) interrupt/dtp source register (eirr) request level setting register (elvr) initial value address : 00003c h 00000000 b initial value address : 00003d h 00000000 b initial value address : 00003e h 00000000 b initial value address : 00003f h 00000000 b 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) er6 er7 er5 er4 er3 er2 er1 er0 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) la3 lb3 lb2 la2 lb1 la1 lb0 la0 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) la7 lb7 lb6 la6 lb5 la5 lb4 la4 mb90335 series 54 block diagram lb7 er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 p60/int0 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p61/int1 p62/int2 sin p63/int3 sot #18(12 h ) * #20(14 h ) * #22(16 h ) * #24(18 h ) * 22222222 p64/int4 sck p65/int5 pwc p66/int6 scl0 p67/int7 sda0 request level setting register (elvr) pin pin pin pin selector selector selector selector selector selector selector selector pin pin pin pin interrupt request signal internal data bus dtp/interrupt source register (eirr) dtp/interrupt enable register (enir) * : interrupt number dtp/external interrupt input detection circuit mb90335 series 55 12. interrupt controller the interrupt control register is located inside the interrupt controller, it exists for every i/o having an interrupt function. this register has the following functions. ? setting of the interrupt levels of relevant peripheral register list note : do not access interrupt control registers using any read modify write instruction because it causes a malfunction. block diagram interrupt control register address icr01 : 0000b1 h icr03 : 0000b3 h icr05 : 0000b5 h icr07 : 0000b7 h icr09 : 0000b9 h icr11 : 0000bb h icr13 : 0000bd h icr15 : 0000bf h icr01 , 03, 05, 07, 09, 11, 13, 15 read/write ? initial value ? address icr00 : 0000b0 h icr02 : 0000b2 h icr04 : 0000b4 h icr06 : 0000b6 h icr08 : 0000b8 h icr10 : 0000ba h icr12 : 0000bc h icr14 : 0000be h icr00, 02, 04, 06, 08, 10, 12, 14 read/write ? initial value ? ( w ) ( 0 ) ( w ) ( 0 ) ( w ) ( 0 ) ( r/w ) ( 0 ) ( r/w ) ( 1 ) ( r/w ) ( 1 ) ( r/w ) ( 1 ) 15 14 13 12 11 10 9 8 ics2 ( w ) ( 0 ) ics3 ics1 ics0 ise il2 il1 il0 ( w ) ( 0 ) ( w ) ( 0 ) ( w ) ( 0 ) ( r/w ) ( 0 ) ( r/w ) ( 1 ) ( r/w ) ( 1 ) ( r/w ) ( 1 ) 76543210 ics2 ( w ) ( 0 ) ics3 ics1 ics0 ise il2 il1 il0 il2 il1 il0 32 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 determine priority of interrupt interrupt request (peripheral resource) (cpu) interrupt level f 2 mc - 16lx bus mb90335 series 56 13. m m m m dmac m dmac is simple dma with the function equal with ei 2 os. it has 16 channels dma transfer channels with the following features. ? performs automatic data transfer between the peripheral resource (i/o) and memory ? the program execution of cpu stops in the dma startup ? capable of selecting whether to increment the transfer source and destination addresses ? dma transfer is controlled by the dma enable register, dma stop status register, dma status register and descriptor ? a stop request is available for stopping dma transfer from the resource ? upon completion of dma transfer, the flag bit corresponding to the transfer completed channel in the dma status register is set and a termination interrupt is output to the transfer controller. register list (continued) dma enable register higher (derh) dma enable register lower (derl) dma stop status register (dssr) dma status register higher (dsrh) dma status register lower (dsrl) dma descriptor channel specification register (dcsr) * : the dssr is lower when the stp bit of dcsr in the dssr is 0. the dssr is upper when the stp bit of dcsr in the dssr is 1. initial value address : 0000ad h 00000000 b initial value address : 0000ac h 00000000 b initial value address : 0000a4 h 00000000 b * initial value address : 00009d h 00000000 b initial value address : 00009c h 00000000 b initial value address : 00009b h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 en14 ( r/w ) en15 en13 en12 en11 en10 en9 en8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 en6 ( r/w ) en7 en5 en4 en3 en2 en1 en0 76543210 stp6 stp14 stp7 stp15 stp5 stp13 stp4 stp12 stp3 stp11 stp2 stp10 stp1 stp9 stp0 stp8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 dte14 dte15 dte13 dte12 dte11 dte10 dte9 dte8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dte6 ( r/w ) dte7 dte5 dte4 dte3 dte2 dte1 dte0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ( r/w ) stp dcsr3 dcsr2 dcsr1 dcsr0 reserved reserved reserved mb90335 series 57 (continued) dma buffer address pointer lower 8 bit (dbapl) dma buffer address pointer middle 8 bit (dbapm) dma buffer address pointer higher 8 bit (dbaph) dma control register (dmacs) dma i/o register address pointer lower 8 bit (dioal) dma i/o register address pointer higher 8 bit (dioah) dma data counter lower 8 bit (ddctl) dma data counter higher 8 bit (ddcth) note : the above register is switched for each channel depending on the dcsr. initial value address : 007920 h xxxxxxxx b initial value address : 007921 h xxxxxxxx b initial value address : 007922 h xxxxxxxx b y initial value address : 007923 h xxxxxxxx b initial value address : 007924 h xxxxxxxx b initial value address : 007925 h xxxxxxxx b initial value address : 007926 h xxxxxxxx b initial value address : 007927 h xxxxxxxx b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dbapl ( r/w ) dbapl dbapl dbapl dbapl dbapl dbapl dbapl 15 14 13 12 11 10 9 8 dbapm dbapm dbapm dbapm dbapm dbapm dbapm dbapm ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dbaph dbaph dbaph dbaph dbaph dbaph dbaph dbaph ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rdy1 rdy2 bytel if bw bf dir se ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 a06 ( r/w ) a07 a05 a04 a03 a02 a01 a00 15 14 13 12 11 10 9 8 a14 a15 a13 a12 a11 a10 a09 a08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 b06 b07 b05 b04 b03 b02 b01 b00 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 b14 b15 b13 b12 b11 b10 b09 b08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) mb90335 series 58 14. address matching detection function when the address is equal to the value set in the address detection register, the instruction code to be read into the cpu is forcibly replaced with the int9 instruction code (01h). as a result, the cpu executes the int9 instruction when executing the set instruction. by performing processing by the int#9 interrupt routine, the program patch function is enabled. two address detection registers are provided, for each of which there is an interrupt enable bit. when the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the cpu is forcibly replaced with the int9 instruction code. register list program address detect register 0 to 2 (padr0) program address detect register 3 to 5 (padr1) program address detect control status register (pacsr) r/w : readable and writable x : undefined padr0 (lower) initial value address : 001ff0 h xxxxxxxx b padr0 (middle) initial value address : 001ff1 h xxxxxxxx b padr0 (higher) initial value address : 001ff2 h xxxxxxxx b padr1 (lower) initial value address : 001ff3 h xxxxxxxx b padr1 (middle) initial value address : 001ff4 h xxxxxxxx b padr1 (higher) initial value address : 001ff5 h xxxxxxxx b pacsr initial value address : 00009e h 00000000 b (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543 210 (r/w) ad1e ad0e reserved reserved reserved reserved reserved reserved mb90335 series 59 15. delay interrupt generator module ? the delay interrupt generation module is a module that generates interrupts for switching tasks. a hardware interrupt can be generated by software. function of delay interrupt generator module block diagram function and control interrupt source setting the r0 bit in the delayed interrupt request generate/cancel register to 1 (dirr: r0 = 1) generates a interrupt request. setting the r0 bit in the delayed interrupt request generate/cancel register to 0 (dirr: r0 = 0) cancels the interrupt request. interrupt control no setting of permission register is provided. interrupt flag set in bit r0 of the delayed interrupt request generation/clear register (dirr : r0) ei 2 os support not ready for expanded intelligent i/o service (ei 2 os). ??????? r0 internal data bus delayed interrupt source/release register (dirr) s interrupt request r latch ? : undefined bit interrupt request signal mb90335 series 60 16. rom mirroring function selection module ? the rom mirror function select module can make a setting so that rom data located in bank ff can be read by accessing bank 00. rom mirroring function selection module block diagram description mirror setting address ffffff h to ff8000 h in the ff bank can be read through 00ffff h to 008000 h in the 00 bank. interrupt source none ei 2 os support not ready for extended intelligent i/o service (ei 2 os). ?????? mi rom internal data bus rom mirror function selection register (romm) 00 bank ff bank address data address area re- served mb90335 series 61 17. low power consumption (standby) mode ?the f 2 mc-16lx can be set to save power consumption by selecting and setting the low power consumption mode. cpu operation mode and functional description register list cpu operating clock operation mode description pll clock normally run the cpu and peripheral resources operate at the clock frequency obtained by pll multiplication of the oscillator clock (hclk) frequency. sleep only peripheral resources operate at the clock frequency obtained by pll multiplication of the oscillator clock (hclk) frequency. time-base timer only the time-base timer operates at the clock frequency obtained by pll multiplication of the oscillator clock (hclk) frequency. stop the cpu and peripheral resources are suspended with the oscillator clock stopped. main clock normally run the cpu and peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. sleep only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. time-base timer only the time-base timer operates at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. stop the cpu and peripheral resources are suspended with the oscillator clock stopped. cpu intermittent operation mode normally run the halved or pll-multiplied oscillator clock (hclk) frequency is used for operation while being decimated in a certain period. lowe power consumption mode control register (lpmcr) initial value address : 0000a0 h 00011000 b ( w ) ( r/w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 slp ( w ) stp spl rst tmd cg1 cg0 reserved mb90335 series 62 18. clock the clock generator controls the internal clock as the operating clock for the cpu and peripheral resources. the internal clock is referred to as machine clock whose one cycle is defined as machine cycle. the clock based on source oscillation is referred to as oscillator clock while the clock based on internal pll oscillation as pll clock. register list clock selection register (ckscr) initial value address : 0000a1 h 11111100 b ( r ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 mcm ( r ) scm ws1 ws0 scs mcs cs1 cs0 mb90335 series 63 19. 512 kbits flash memory the description that follows applies to the flash memory built in the mb90f334; it is not applicable to evaluation rom or masked rom. the method of data write/erase to flash memory is following three types. parallel writer serial dedicated writer write/erase by executing program ? description of 512 kbits flash memory 512 kbits flash memory is located in ff h bank in the cpu memory map. function of flash memory interface circuit enables read and program access from cpu. write/erase to flash interface is executed by instruction from cpu via flash memory interface, so rewrite of program and data is carried on in the mounting state effectively. data can be reprogrammed not only by program execution in existing ram but by program execution in flash memory by dual operation. the different banks (the upper and lower banks) can be used to execute an erase/ program and a read concurrently. also, erase/write and read in the defferent bank (upper bank/lower bank) is executed simultaneously. ? features of 512 kbits flash memory sector configuration : 64 kwords 8 bits/32 words 16 bits (4k 4 + 16k 2 + 4k 4) simultaneous execution of erase/write and read by 2-bank configuration automatic program algorithm (embeded algorithm tm *) built-in deletion pause/deletion resume function detection of programming/erasure completion using data polling and the toggle bit at least 10,000 times guaranteed minimum flash read cycle time : 2 machine cycles * : embedded algorithm tm is a trade mark of advanced micro devices inc. note : the read function of manufacture code and device coad is not including. also, these code is not accessed by the command. flash write/erase flash memory can not execute write/erase and read by the same bank simultaneously. data can be programmed/deleted into and erased from flash memory by executing either the program residing in the flash memory or the one copied to ram from the flash memory. mb90335 series 64 sector configuration of flash memoly sa0 (4 kbyte) sa1 (4 kbyte) sa2 (4 kbyte) sa3 (4 kbyte) ff0000 h ff0fff h ff1000 h ff1fff h ff2000 h ff2fff h 70000 h 70fff h 71000 h 71fff h 72000 h 72fff h sa4 (16 kbyte) sa5 (16 kbyte) sa6 (4 kbyte) ff3000 h ff3fff h ff4000 h ff7fff h ff8000 h ffbfff h ffc000 h ffcfff h 73000 h 73fff h 74000 h 77fff h 78000 h 78fff h 7c000 h 7cfff h sa7 (4 kbyte) sa8 (4 kbyte) sa9 (4kbyte) ffd000 h ffdfff h ffe000 h ffefff h fff000 h ffffff h 7d000 h 7dfff h 7e000 h 7efff h 7f000 h 7ffff h lower bank upper bank flash memory cpu address writer address * * : flash memory writer address indicates the address equivalent to the cpu address when data is written to the flash memory using a parallel writer. programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. mb90335 series 65 register list flash memory control register (fmcs) flash memory program control register (fwr0) flash memory program control register (fwr1) sector conversion setting register (ssr0) * when writing to ssr0 register, write ?0? except for sen0. initial value address : 0000ae h 000x0000 b initial value address : 00790c h 00000000 b initial value address : 00790d h 00000000 b initial value address : 00790e h 00xxxxx0 b ( r/w ) ( r/w ) ( r ) ( w ) ( r/w ) ( w ) ( r/w ) 76543210 rdyint ( r/w ) inte we rdy lpm1 lpm0 reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 sa6e ( r/w ) sa7e sa5e sa4e sa3e sa2e sa1e sa0e ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 0 ? ( r/w ) ???? ? sa9e sa8e ( r/w ) ( ? )( ? )( ? )( ? )( ? ) ( r/w ) 76543210 ? ( r/w ) ???? ?? sen0 mb90335 series 66 standard configuration for fujitsu standard serial on-board writing the flash microcontroller programmer (af220/af210/af120/af110) made by yokogawa digital computer corp. is used for fujitsu standard serial onboard writing. note : inquire of yokogawa digital computer corporation for details about the functions and operations of the flash microcontroller programmer (af220, af210, af120 and af110) , general-purpose common cable for connection (az210) and connectors. pins used for fujitsu standard serial on-board programming pin function description md2, md1, md0 mode input pin the device enters the serial program mode by setting md2 = 1, md1 = 1 and md0 = 0. x0, x1 oscillation pin because the internal cpu operation clock is set to be the 1 multiplication pll clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. p60, p61 write program start pins input a low level to p60 and a high level to p61. rst reset input pin ? sin0 serial data input pin uart0 is used as clk synchronous mode. in write mode, the pins used for the uart0 clk synchronous mode are sin0, sot0, and sck0. sot0 serial data output pin sck0 serial clock input pin v cc power source input pin when supplying the write voltage (mb90f337 : 3.3 v 0.3 v) from the user system, connection with the flash microcontroller programmer is not necessary. when connecting, do not short-circuit with the user power supply. v ss gnd pin share gnd with the flash microcontroller programmer. rs232c host interface cable (az201) general-purpose common cable (az210) clk synchronous serial mb90f337 user system can operate standalone flash microcontroller programmer + memory card mb90335 series 67 the control circuit shown in the diagram is required for using the p60, p61, sin0, sot0 and sck0 pins on the user system. isolate the user circuit during serial on-board writing, with the /tics signal of the flash microcon- troller programmer. control circuit the mb90f337 serial clock frequency that can be input is determined by the following expression use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock frequency to be used. imputable serial clock frequency = 0.125 oscillation clock frequency. maximum serial clock frequency system configuration of the flash microcontroller programmer (af220/af210/af120/af110) (made by yokogawa digital computer corp.) contact to : yokogawa digital computer corp. tel : (81)-42-333-6224 note : the af200 flash micon programmer is a retired product, but it can be supported using control module ff201. oscillation clock frequency maximum serial clock frequency acceptable to the microcontroller maximum serial clock frequency that can be set with the af220/af210/ af120/af110 maximum serial clock frequency that can be set with the af200 at 6 mhz 750 khz 500 khz 500 khz part number function unit af220/ac4p model with internal ethernet interface /100 v to 220 v power adapter af210/ac4p standard model /100 v to 220 v power adapter af120/ac4p single key internal ethernet interface mode /100 v to 220 v power adapter af110/ac4p single key model /100 v to 220 v power adapter az221 pc/at rs232c cable for writer az210 standard target probe (a) length : 1 m ff201 control module for fujitsu f 2 mc-16lx flash microcontroller control module az290 remote controller /p2 2 mb pc card (option) flash memory capacity to respond to 128 kb /p4 4 mb pc card (option) flash memory capacity to respond to 512 kb 10 k w af220/af210/af120/af110 write control pin af220/af210/af120/af110 /tics pin mb90f337 write control pin user mb90335 series 68 n n n n electrical characteristics 1. absolute maximum ratings (v cc = 3.3 v , v ss = 0.0 v) *1 : v i and v o must not exceed v cc + 0.3 v. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *2 : a peak value of an applicable one pin is specified as a maximum output current. *3 : the average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *4 : the average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 4.0 v input voltage v i v ss - 0.3 v ss + 4.0 v *1 v ss - 0.3 v ss + 6.0 v nch0.d (withstand voltage i/o of 5 v) - 0.5 v ss + 4.5 v usb i/o output voltage v o v ss - 0.3 v ss + 4.0 v *1 - 0.5 v ss + 4.5 v usb i/o l level maximum output current i ol1 ? 10 ma other than usb i/o* 2 i ol2 ? 43 ma usb i/o* 2 l level average output cur- rent i olav ? 3ma*3 l level maximum total out- put current s i ol ? 60 ma l level average total output current s i olav ? 30 ma *4 h level maximum output current i oh1 ? - 10 ma other than usb i/o* 2 i oh2 ? - 43 ma usb i/o* 2 h level average output cur- rent i ohav ? - 3ma*3 h level maximum total out- put current s i oh ? - 60 ma h level average total output current s i ohav ? - 30 ma *4 power consumption pd ? 351 mw target value operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c - 55 + 125 c usb i/o mb90335 series 69 2. recommended operating conditions (v ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 3.6 v at normal operation (at usb is used) 2.7 3.6 v at normal operation (at usb is unused) 1.8 3.6 v hold state of stop operation input h level voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihm v cc - 0.3 v cc + 0.3 v md input pin v ihusb 2.0 v cc + 0.3 v usb input pin input l level voltage v il v ss - 0.3 0.3 v cc v cmos input pin v ils v ss - 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss - 0.3 v ss + 0.3 v md input pin v ilusb v ss 0.8 v usb input pin differential input sensitivity v di 0.2 ? v usb input pin differential common mode input voltage range v cm 0.8 2.5 v usb input pin series resistance r s 25 30 w recommended value = 27 w at using usb operating temperature t a - 40 + 85 c at usb is unused 0 + 70 cat usb is used mb90335 series 70 3. dc characteristics (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) note : p60 to p67 are n-ch open-drain pins usually used as cmos. parameter sym- bol pin name conditions value unit remarks min typ max output h level voltage v oh output pin of other than p60 to p67, hvp, hvm, dvp, dvm i oh = - 4.0 ma v cc - 0.5 ? vcc v hvp, hvm, dvp, dvm rl = 15 k w 5 % 2.8 ? 3.6 v output l level voltage v ol output pin of other than hvp, hvm, dvp, dvm i ol = 4.0 ma vss ? vss + 0.4 v hvp, hvm, dvp, dvm rl = 1.5 k w 5 % 0 ? 0.3 v input leak current i il output pin of other than p60 to p67, hvp, hvm, dvp, dvm v cc = 3.3 v, vss < v i < v cc - 10 ? 10 m a hvp, hvm, dvp, dvm ?- 5 ? 5 m a pull-up resistor r pull p00 to p07, p10 to p17 v cc = 3.3 v, ta = + 25 c 25 50 100 k w open drain output current i liod p60 to p67 ?? 0.1 10 m a power supply current i cc v cc v cc = 3.3 v, internal frequency 24 mhz, at normal operating ? tbd ? ma at usb operating max 90 ma (target) v cc = 3.3 v, internal frequency 24 mhz, at normal operating ? 70 ? ma at non- operating usb (ustp = 0) v cc = 3.3 v, internal frequency 24 mhz, at normal operating ? tbd ? ma at non- operating usb (ustp = 1) i ccs v cc = 3.3 v, internal frequency 24 mhz, at sleep mode ? 27 ? ma i cts v cc = 3.3 v, internal frequency 24 mhz, at timer mode ? 3.5 ? ma v cc = 3.3 v, internal frequency 3 mhz, at timer mode ? 1 ? ma i cch ta = + 25 c, at stop mode ? 1 ?m a input capacitance c in other than vcc and vss ?? 515pf pull-up resistor r up rst ? 25 50 100 k w mb90335 series 71 4. ac characteristics (1) clock input timing (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) parameter sym- bol pin name value unit remarks min typ max clock frequency f ch x0, x1 ? 6 ? mhz external crystal oscillation 6 ? 24 mhz external clock input clock cycle time t hcyl x0, x1 ? 166.7 ? ns external crystal oscillation 166.7 ? 41.7 ns external clock input input clock pulse width p wh p wl x0 10 ?? ns a reference duty ratio is 30 % to 70 % . input clock rise time and fall time tcr tcf x0 ?? 5 ns at external clock internal operating clock frequency f cp ? 3 ? 24 mhz at main clock is used internal operating clock cycle time t cp ? 42 ? 333 ns at main clock is used 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 clock timing mb90335 series 72 the ac standards provide that the following measurement reference voltages. pll operation guarantee range relation between internal operation clock frequency and power supply voltage * : when the usb is used, operation is guaranteed at voltages between 3.0 v to 3.6 v. relation between oscillation frequency and internal operation clock frequency 3.6 3.0 2.7 3 6 12 24 internal clock f cp (mhz) power supply voltage v cc (v) pll operation guarantee range normal operation assurance range 3 12 6 6 24 24 internal clock f cp (mhz) oscillation clock f c (mhz) multiply by 4 multiply by 2 multiply by 1 external clock 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc input signal waveform hysteresis input pin hysteresis input/other than md input pin output signal waveform output pin mb90335 series 73 (2) reset (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * : oscillation time of oscillator is the time that the amplitude reaches 90 %. it takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a far/ceramic oscillator, and 0 milliseconds on an external clock. parameter sym- bol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 500 ? ns at normal operating, at time base timer mode, at main sleep mode, at pll sleep mode oscillation time of oscillator* + 500 ns ?m s at stop mode rst x0 500 ns t rstl 0.2 v cc 0.2 v cc rst t rstl 0.2 v cc 0.2 v cc in stop mode internal operation clock internal reset oscillation time of oscillator oscillation stabilization wait time execute instruction 90 % of amplitude during normal operation, in time-base timer mode, in main sleep mode and in pll sleep mode mb90335 series 74 (3) power-on reset (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) notes : v cc must be lower than 0.2 v before the power supply is turned on. the above standard is a value for performing a power - on reset. in the device, there are internal registers which is initialized only by a power-on reset. when the initial ization of these items is expected, turn on the power supply according to the standards. parameter symbol pin name condi- tions value unit remarks min max power supply rising time t r v cc ? ? 30 ms power supply shutdown time t off v cc 1 ? ms for repeated operation v cc v cc 3.0 v v ss t r 0.2 v 0.2 v 2.7 v t off 0.2 v sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. when raising the power, do not use pll clock. however, if voltage drop is 1 v/s or less, use of pll clock is allowed during operation. ram data hold the rising edge should be 50 mv/ms or less. mb90335 series 75 (4) uart0, uart1 i/o extended serial timing (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) notes : ac rating in clk synchronous mode. c l is a load capacitance value on pins for testing. t cp is the machine cycle period (unit : ns) . parameter sym- bol pin name conditions value unit remarks min max serial clock cycle time t scyc sckx internal shiftc lock mode output pin is c l = 80 pf + 1 ttl 8 t cp ? ns sck ? sot delay time t slov sckx sotx - 80 80 ns valid sin ? sck - t ivsh sckx sinx 100 ? ns sck - ? valid sin hold time t shix sckx sinx 60 ? ns serial clock h pulse width t shsl sckx, sinx external shift clock mode output pin is c l = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh sckx, sinx 4 t cp ? ns sck ? sot delay time t slov sckx sotx ? 150 ns valid sin ? sck - t ivsh sckx sinx 60 ? ns sck - ? valid sin hold time t shix sckx sinx 60 ? ns internal shift clock mode external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90335 series 76 (5) i 2 c timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = - 40 c to + 85 c) parameter sym- bol pin name condi- tions value unit remarks min max scl clock frequency f scl ? ? 0 100 khz bus-free time between stop and start conditions t bus ? 4.7 ?m s hold time (resend) start t hdsta ? 4.0 ?m s the first clock pulse is generated immediately after the period. scl clock ?l? status hold time t low ? 4.7 ?m s scl clock ?h? status hold time t high ? 4.0 ?m s resend start condition setup time t susta ? 4.7 ?m s data hold time t hddat ? 0 ?m s data set-up time t sudat ? 40 ? ns sda and scl signal rise time t r ?? 1000 ns sda and scl signal fall time t f ?? 300 ns stop condition setup time t susto ? 4.0 ?m s sda scl t bus t hdsta t hddat t sudat t susta t susto t low t high t hdsta 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t r t f f scl mb90335 series 77 (6) timer input timing (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) (7) timer output timing (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) (8) trigger input timing (t a = - 40 c to + 85 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) parameter symbol pin name condi- tions value unit remarks min max input pulse width t tiwh t tiwl pwc ? 4 t cp ? ns parameter sym- bol pin name condi- tions value unit remarks min max clk - ? t out change time ppg0 to ppg3 change time t to ppgx ? 30 ? ns parameter symbol pin name condi- tions value unit remarks min max input pulse width t trgh t trgl intx ? 5 t cp ? ns at normal operating 1 ?m s at stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl pwc clk ppgx 2.4 v t to 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl intx mb90335 series 78 5. usb characteristics (t a = 0 c to + 70 c, v cc = 3.3 v 0.3 v, v ss = 0.0 v) data signal timing (full speed) data signal timing (low speed) parameter symbol sym bol value unit remarks min max input characteristics input high level voltage v ih 2.0 ? v input low level voltage v il ? 0.8 v differential input sensitivity v di 0.2 ? v differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 3.6 v i oh = - 200 m a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross over voltage v crs 1.3 2.0 v rise time t fr 4 20 ns full speed t lr 75 300 ns low speed fall time t ff 4 20 ns full speed t lf 75 300 ns low speed rising/falling time matching t rfm 90 111.11 % (t fr /t ff ) t rlm 80 125 % (t lr /t lf ) output registance z drv 28 44 w including rs = 27 w dvm/hvm 90% t fr 10% 90% 10% t ff vcrs dvp/hvp rise time fall time hvp 90% t lr 10% 90% 10% tlf vcrs hvm rise time fall time mb90335 series 79 load condition (full speed) load condition (low speed) dvp/hvp r s = 27 w c l = 50 pf dvm/hvm rs = 27 w c l = 50 pf testing point testing point hvp r s = 27 w c l = 50 pf ~ 150 pf hvm r s = 27 w c l = 50 pf ~ 150 pf testing point testing point mb90335 series 80 n n n n ordering information mb90335 series part number package remarks mb90f337pfm MB90337pfm 64-pin plastic lqfp (fpt-64p-m09) mb90335 series 81 n n n n package dimension 64-pin plastic lqfp (fpt-64p-m09) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f64018s-c-3-5 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.000.10(.472.004)sq 14.000.20(.551.008)sq index 0.320.05 (.013.002) m 0.13(.005) 0.1450.055 (.0057.0022) "a" .059 C.004 +.008 C0.10 +0.20 1.50 0~8 ? 0.25(.010) (mounting height) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) details of "a" part (stand off) 0.10(.004) * mb90335 series 82 memo mb90335 series 83 memo mb90335 series fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0312 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-party?s intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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